41using namespace SVFUtil;
102 std::vector<Condition>
condVec;
149 BBCondMap::const_iterator
it =
bbConds.find(bb);
150 assert(
it !=
bbConds.end() &&
"basic block does not have branch and conditions??");
151 CondPosMap::const_iterator
cit =
it->second.find(
pos);
152 assert(
cit !=
it->second.end() &&
"no condition on the branch??");
192 if (
condVar->isConstDataOrAggDataButNotNullPtr())
271 if (
svffun->isLoopHeader(bb))
274 std::vector<const SVFBasicBlock*>
exitbbs;
312 for (
const auto &
svfStmt: icfgNode->getSVFStmts())
355 if(!test)
return false;
368 if(!test)
return false;
404 if (SVFUtil::isa<ConstantNullPtrValVar>(
op1))
410 inDirVal.insert(
it->getDstNode()->getValue());
414 else if (SVFUtil::isa<ConstantNullPtrValVar>(
op0))
420 inDirVal.insert(
it->getDstNode()->getValue());
435 if (
const CallICFGNode* cs = SVFUtil::dyn_cast<CallICFGNode>(icfgNode))
453 for (
const auto &bit:
it->second)
523 assert(
srcBB->getParent() ==
dstBB->getParent() &&
"two basic blocks are not in the same function??");
529 worklist.push(
srcBB);
532 while (!worklist.empty())
556 ") --> " <<
"succ_bb (" <<
succ->getName() <<
") condition: " <<
brCond <<
"\n");
577 outs() <<
"print path condition\n";
621 return res == z3::unsat;
644 if (condition.
getExpr().num_args() == 0)
645 if (!condition.
getExpr().is_true() && !condition.
getExpr().is_false())
#define DBOUT(TYPE, X)
LLVM debug macros, define type of your DBUG model of each pass.
static u32_t maximumCxtLen
static u32_t maximumPathLen
static u64_t maximumBudget
const GEdgeSetTy & getOutEdges() const
static const Option< bool > PrintPathCond
const SVFFunction * getParent() const
const std::vector< const ICFGNode * > & getICFGNodeList() const
const std::vector< const SVFBasicBlock * > & getSuccessors() const
u32_t getBBSuccessorPos(const SVFBasicBlock *succbb)
u32_t getNumSuccessors() const
const ICFGNode * back() const
const_iterator end() const
const_iterator begin() const
std::vector< constSVFBasicBlock * >::const_iterator const_iterator
const SVFBasicBlock * getEntryBlock() const
CallGraph * getCallGraph()
SVFStmtList & getSVFStmtList(const ICFGNode *inst)
Given an instruction, get all its PAGEdges.
static SVFIR * getPAG(bool buildFromFile=false)
Singleton design here to make sure we only have one instance during any analysis.
const std::string & getName() const
void allocate(const SVFModule *module)
Perform path allocation.
virtual void allocateForBB(const SVFBasicBlock &bb)
Allocate path condition for every basic block.
std::string dumpCond(const Condition &cond) const
Condition newCond(const ICFGNode *inst)
Allocate a new condition.
Condition evaluateTestNullLikeExpr(const BranchStmt *branchStmt, const SVFBasicBlock *succ)
Return branch condition after evaluating test null like expression.
Condition evaluateProgExit(const BranchStmt *branchStmt, const SVFBasicBlock *succ)
Return condition when there is a branch calls program exit.
Condition condOr(const Condition &lhs, const Condition &rhs)
bool isTestContainsNullAndTheValue(const CmpStmt *cmp) const
Return true if two values on the predicate are what we want.
bool isTestNullExpr(const ICFGNode *test) const
Return true if this is a test null expression.
void printPathCond()
Print out the path condition information.
bool postDominate(const SVFBasicBlock *bbKey, const SVFBasicBlock *bbValue) const
SaberCondAllocator()
Constructor.
void setBranchCond(const SVFBasicBlock *bb, const SVFBasicBlock *succ, const Condition &cond)
Get/Set a branch condition, and its terminator instruction.
virtual Condition getPHIComplementCond(const SVFBasicBlock *BB1, const SVFBasicBlock *BB2, const SVFBasicBlock *BB0)
BBCondMap bbConds
map basic block to its successors/predecessors branch conditions
Condition condNeg(const Condition &cond)
static u32_t totalCondNum
vector storing z3expression
Condition condAnd(const Condition &lhs, const Condition &rhs)
Condition operations.
bool isSatisfiable(const Condition &condition)
whether condition is satisfiable
Condition getBranchCond(const SVFBasicBlock *bb, const SVFBasicBlock *succ) const
Get branch condition.
virtual Condition ComputeInterRetVFGGuard(const SVFBasicBlock *src, const SVFBasicBlock *dst, const SVFBasicBlock *retBB)
const SVFGNode * getCurEvalSVFGNode() const
Get current value for branch condition evaluation.
Condition getFalseCond() const
bool setCFCond(const SVFBasicBlock *bb, const Condition &cond)
Get/Set control-flow conditions.
void collectBBCallingProgExit(const SVFBasicBlock &bb)
Collect basic block contains program exit function call.
bool isBBCallsProgExit(const SVFBasicBlock *bb)
void extractSubConds(const Condition &condition, NodeBS &support) const
extract subexpression from a Z3 expression
Map< u32_t, Condition > CondPosMap
id to instruction map for z3
bool isEquivalentBranchCond(const Condition &lhs, const Condition &rhs) const
Whether lhs and rhs are equivalent branch conditions.
bool isEQCmp(const CmpStmt *cmp) const
Evaluate test null/not null like expressions.
bool isNECmp(const CmpStmt *cmp) const
Return true if the predicate of this compare instruction is not equal.
Condition evaluateBranchCond(const SVFBasicBlock *bb, const SVFBasicBlock *succ)
Evaluate branch conditions.
Condition evaluateLoopExitBranch(const SVFBasicBlock *bb, const SVFBasicBlock *succ)
Evaluate loop exit branch.
Condition getTrueCond() const
FIFOWorkList< const SVFBasicBlock * > CFWorkList
worklist for control-flow guard computation
bool isTestNotNullExpr(const ICFGNode *test) const
Return true if this is a test not null expression.
Condition getCFCond(const SVFBasicBlock *bb) const
FunToExitBBsMap funToExitBBsMap
map a function to all its basic blocks calling program exit
bool isNegCond(u32_t id) const
Condition getEvalBrCond(const SVFBasicBlock *bb, const SVFBasicBlock *succ)
Get a condition, evaluate the value for conditions if necessary (e.g., testNull like express)
virtual Condition ComputeInterCallVFGGuard(const SVFBasicBlock *src, const SVFBasicBlock *dst, const SVFBasicBlock *callBB)
void setNegCondInst(const Condition &condition, const ICFGNode *inst)
mark neg Z3 expression
bool dominate(const SVFBasicBlock *bbKey, const SVFBasicBlock *bbValue) const
void setCondInst(const Condition &condition, const ICFGNode *inst)
virtual Condition ComputeIntraVFGGuard(const SVFBasicBlock *src, const SVFBasicBlock *dst)
Guard Computation for a value-flow (between two basic blocks)
std::vector< Condition > conditionVec
bit vector for distinguish neg
virtual const SVFValue * getValue() const
Return the corresponding LLVM value, if possible, nullptr otherwise.
const z3::expr & getExpr() const
static z3::solver & getSolver()
Get z3 solver, singleton design here to make sure we only have one context.
static Z3Expr NEG(const Z3Expr &z3Expr)
compute NEG
static z3::expr nullExpr()
null expression
static z3::context & getContext()
Get z3 context, singleton design here to make sure we only have one context.
bool isExtCall(const SVFFunction *fun)
std::string pasMsg(const std::string &msg)
Print each pass/phase message by converting a string into blue string output.
bool isProgExitCall(const CallICFGNode *cs)
std::ostream & outs()
Overwrite llvm::outs()
llvm::IRBuilder IRBuilder